Sensing circuit for memory cells
US6535428B2 · kind B2 · utility
21Cited by
2References
58Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2001 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Jun 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.