Architecture and scheme for a non-strobed read sequence
US6535434B2 · kind B2 · utility
63Cited by
14References
46Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2001 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Apr 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture and method for implementing a non-strobed operation on an array cell within a memory array in which a reference unit is provided for emulating the response of an array cell during a desired operation, for example, a read, program verify, erase verify or other types of read operations. The reference unit includes a reference cell which is driven by a non-strobed gate voltage. The architecture and method permit relatively noise-free array cell interrogations at close to ground voltage levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.