Incorporation of critical dimension measurements as disturbances to lithography overlay run to run controller
US6535774B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1999 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Aug 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67276
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention, in its various aspects, is a method and apparatus for processing a semiconductor wafer. The method, in one embodiment, comprises processing a wafer lot through an exposure tool; identifying a disturbance in an overlay operation arising from critical dimension control of the exposure tool; modeling the identified disturbance; and applying the model to modify an overlay input parameter. The invention, in another aspect, is an apparatus for controlling a photolithography process. The apparatus comprising an exposure tool and a computer. The exposure tool includes an overlay controller capable of receiving a plurality of overlay control inputs and a critical dimension controller. The computer receives data from the exposure tool and is programmed to perform a method. The programmed method includes identifying a disturbance in an overlay operation arising from critical dimension control of the exposure tool; modeling the identified disturbance; and applying the model to modify an overlay control input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.