System and method for prefetching data using a hardware prefetch mechanism
US6535962B1 · kind B1 · utility
24Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 1999 |
| Grant date | Mar 18, 2003 |
| Priority date | — |
| Expiry date | Nov 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.