Packaging substrate comprising staggered vias
US6538307B1 · kind B1 · utility
2Cited by
9References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2001 |
| Grant date | Mar 25, 2003 |
| Priority date | — |
| Expiry date | Jan 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging substrate is formed with staggered vias interconnecting fan-out circuitry for improved strength and rigidity. Embodiments of the present invention include substrates wherein less than 20% of the vias are aligned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.