Silicon epitaxial wafer and a method for producing it
US6541117B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 16, 2000 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Jan 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3225
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is disclosed a silicon epitaxial wafer comprising an epitaxial layer formed on a silicon wafer wherein Erratic phenomenon does not occur in a MOS device fabricated on the silicon epitaxial wafer, a silicon epitaxial wafer having oxide dielectric breakdown voltage of 20 MV/cm or more, a silicon epitaxial wafer comprising an epitaxial layer formed on a silicon wafer wherein oxygen concentration at an interface between the epitaxial layer and the silicon wafer of the silicon epitaxial wafer is 1×1017 to 1×1018 atoms/cm3 or 5×1016 to 5×1017 atoms/cm3, a method for producing a silicon epitaxial wafer comprising subjecting a silicon wafer to heat treatment in a hydrogen atmosphere, and then growing an epitaxial layer on the silicon wafer wherein the initial oxygen concentration of the silicon wafer, the heat treatment temperature and the heat treatment time of the heat treatment are predetermined so that oxygen concentration at an interface between the epitaxial layer and the silicon wafer of the silicon epitaxial wafer may be 1×1017 to 1×1018 atoms/cm3 or 5×1016 to 5×1017 atoms/cm3. There is provided a silicon epitaxial wafer compris…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.