Method of forming a semiconductor array of floating gate memory cells having strap regions and a peripheral logic device region
US6541324B1 · kind B1 · utility
54Cited by
27References
13Claims
0Family size
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Key dates
| Filing date | Apr 30, 2002 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Apr 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/43
Abstract
A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array and a peripheral region adjacent the array containing related logic devices. Structure planarization is enhanced by utilizing a pattern of dummy material in the peripheral region. The control gates of the memory cells and the logic gates of the logic devices are formed separately so each can be independently optimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.