Method for limiting divot formation in post shallow trench isolation processes
US6541351B1 · kind B1 · utility
30Cited by
17References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Nov 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for limiting divot formation in shallow trench isolation structures. The method includes: providing a trench formed in a silicon region with a deposited oxide; oxidizing a top layer of the silicon region to form a layer of thermal oxide on top of the silicon region; and selectively etching the thermal oxide with respect to the deposited oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.