Method and apparatus for reducing fixed charges in a semiconductor device
US6541369B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1999 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Dec 7, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/952
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing trapped charges in a semiconductor device having a first layer and a second layer, said method comprising the steps of providing said first layer, flowing a deposition, a dilution and a conversion gas upon said first layer thereby forming a transition layer, phasing out said flow of conversion gas and forming said second layer upon said transition layer. The deposition gas, dilution gas and conversion gas are preferably trimethylsilane, helium and N2O respectively. The method is performed via chemical vapor deposition or plasma enhanced chemical vapor deposition. The apparatus has a first insulating layer, a transition layer disposed upon said first layer and a second insulating layer disposed upon said transition layer. The transition layer improves the adhesion between said first insulating layer and said second insulating layer. A reduction in the amount of electrical charges (i.e., ions, electrons or the like) trapped between layers of deposited material improves the integrity and quality of devices formed from such layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.