Modified vertical MOSFET and methods of formation thereof

US6541810B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ramachandra Divakaruni · Ossining, US
• Prakash Dev · Plano, US
• Rajeev Malik · Pleasantville, US
• Larry Nesbit · Farmington, US

Key dates

• Filing date: Jun 29, 2001
• Grant date: Apr 1, 2003
• Expiry date: Jun 29, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488

Abstract

The vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with both the bitline diffusion region and shallow trench isolation region. The vertical gate polysilicon is isolated from both the bitline diffusion and shallow trench isolation region by the nitride spacer, which provides reduced bitline capacitance and reduced incidence of bitline diffusion to vertical gate shorts.