Low voltage planar power MOSFET with serpentine gate pattern
US6541820B1 · kind B1 · utility
77Cited by
24References
7Claims
0Family size
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Inventor
Key dates
| Filing date | Mar 28, 2000 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Mar 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
Abstract
A three mask process is described for a low voltage, low on-resistance power MOSFET. A serpentine gate divides a non-epi silicon die into laterally separated drain and source regions with a very large channel width per unit area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.