Barrier-to-seed layer alloying in integrated circuit interconnects
US6541860B1 · kind B1 · utility
4Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2001 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Jun 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and a method for manufacture thereof are provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. An opening is formed in the dielectric layer. A barrier layer with an alloying element is deposited to line the opening in the dielectric layer. A conductor core is deposited on the barrier layer to fill the opening and connect to the semiconductor device. The conductor core is annealed causing migration of the alloy element into the conductor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.