Semiconductor device having a reduced signal processing time and a method of fabricating the same

US6541863B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Manfred Horstmann · Dresden, DE
• Karsten Wieczorek · Dresden, DE
• Gert Burbach · Dresden, DE

Key dates

• Filing date: Jan 5, 2000
• Grant date: Apr 1, 2003
• Expiry date: Jan 5, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

There is provided a semiconductor device comprising an insulating layer which is partly formed of porous material, and a method for fabricating the device. A stray capacitance of adjacent wiring lines is significantly reduced by reducing the amount of material, i.e., by using porous material in the insulating layer of a metallization layer. In one embodiment, the porous layer may be fabricated separately on a further substrate and is subsequently transferred to the product wafer while the further substrate and the product wafer are appropriately aligned to each other. In this way, fabrication of complete metallization layers having a reduced dielectric constant in advance or concurrently with the product wafer carrying the MOS structure is possible. Due to the reduced capacitance of the wiring lines of the metallization layer, signal performance and/or power consumption of an integrated circuit is improved.