Scheduler capable of issuing and reissuing dependency chains
US6542984B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2000 |
| Grant date | Apr 1, 2003 |
| Priority date | — |
| Expiry date | Jan 3, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38585
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scheduler issues instruction operations for execution, but also retains the instruction operations. If a particular instruction operation is subsequently found to be incorrectly executed, the particular instruction operation may be reissued from the scheduler. The penalty for incorrect scheduling of instruction operations may be reduced as compared to purging the particular instruction operation and younger instruction operations from the pipeline and refetching the particular instruction operation. Furthermore, the scheduler may employ a more aggressive scheduling mechanism since the penalty for incorrect execution is reduced. Additionally, the scheduler maintains the dependency indications for each instruction operation which has been issued. If the particular instruction operation is reissued, the instruction operations which are dependent on the particular instruction operation (directly or indirectly) may be identified via the dependency indications. The scheduler reissues the dependent instruction operations as well. Instruction operations which are subsequent to the particular instruction operation in program order but which are not dependent on the particular instruction …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.