Method for fabricating MOSFET device
US6544822B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Jun 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a MOSFET device having a metal gate with an ultra shallow junction and allowing the application of a self-aligned contact. A sacrificial gate is formed on a silicon substrate, as is a first silicon epitaxial layer, which is thinner than the sacrificial gate. Elevated source/drain regions are formed on the silicon substrate by implanting desired impurity ions. An interlayer insulating film is deposited over the resultant structure and polished to expose the sacrificial gate. A groove is formed in which a gate insulating film and a metal film are deposited. The metal film, the gate insulating film and the interlayer insulating film are polished until the first silicon epitaxial layer is exposed. A second silicon epitaxial layer is then formed on the first silicon epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.