Single poly non-volatile memory structure and its fabricating method
US6544847B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Jul 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
Abstract
The present invention discloses a method for fabricating a non-volatile memory structure from a single layer of polysilicon in a semiconductor substrate, wherein the semiconductor substrate with two active areas, first and second, are divided by isolation regions. In accordance with this method, a doped buried layer is formed in the first active area. Then, a first floating gate is formed on the buried layer and a second floating gate is formed on the second active area from the single layer of polysilicon. Next, two doped regions are formed at opposite sides of the second floating gate in the second active areas. Finally, a floating gate connection line is employed to connect the first and second floating gate for making sure that the two floating gates are in the same potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.