Fuse circuit configuration
US6545526B2 · kind B2 · utility
7Cited by
5References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 29, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Sep 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fuse circuit configuration is described wherein a compensation capacitor counteracts a parasitic capacitor. The parasitic capacitor occurs between a connection point of a switching transistor and a fuse and ground. The compensation capacitor is connected to an evaluation circuit. In this manner, the negative effects caused by the parasitic capacitor are compensated for.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.