MRAM module configuration
US6545900B2 · kind B2 · utility
10Cited by
5References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Sep 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An MRAM module configuration in which, in order to increase the packing density, memory cell zones containing memory arrays and peripheral circuits are nested in one another. In this manner, an increased packing density of the memory cell is achieved which results in lowered production costs and a smaller chip space for a more compact configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.