6F2 DRAM ARRAY, A DRAM ARRAY FORMED ON A SEMICONDUCTIVE SUBSTRATE, A METHOD OF FORMING MEMORY CELLS IN A 6F2 DRAM ARRAY AND A METHOD OF ISOLATING A SINGLE ROW OF MEMORY CELLS IN A 6F2 DRAM ARRAY

US6545904B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventor

• Luan C. Tran · Meridian, US

Key dates

• Filing date: Mar 16, 2001
• Grant date: Apr 8, 2003
• Expiry date: Mar 27, 2021

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/981

Abstract

The present invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate has a gate dielectric having a second thickness that is greater than the first thickness. The isolation gate dielectric may extend above or below a surface of the substrate.