Flash memory erase method
US6545911B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2001 |
| Grant date | Apr 8, 2003 |
| Priority date | — |
| Expiry date | Aug 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An flash memory erase method. A bias Vg is applied to a gate of a memory cell. A bias Vd is applied to a source/drain region of the memory cell to execute an erase operation. The bias Vd is increased from an initial value to a predetermined value over time. During the increase of the bias Vd, no inspection is performed. Whether the memory of each memory cell has been erased is inspected. If the erase operation is complete, the erase operation is over. If not, a voltage raise erase-inspection step is performed at least once until it is confirmed that the memory of all the memory cells has been erase. Each voltage raise erase-inspection step includes an erase step with a raised voltage and an inspection step afterwards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.