SOI MOSFET and method of fabrication
US6548361B1 · kind B1 · utility
49Cited by
12References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2002 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | May 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOSFET formed in semiconductor-on-insulator format. The MOSFET includes a source and a drain formed in a layer of semiconductor material, each having an extension region and a deep doped region. A body is formed between the source and the drain and includes a first damaged region adjacent the extension of the source and a second damaged region adjacent the extension of the drain. The first and second damaged regions include defects caused by amorphization of the layer of semiconductor material. A gate electrode, the source, the drain and the body are operatively arranged to form a transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.