Method to fabricate MIM capacitor with a curvillnear surface using damascene process
US6548367B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2002 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Apr 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
Abstract
In one method embodiment, the present invention recites forming an opening in a substrate during a damascene process. The present embodiment then recites forming a dielectric region having two curvilinear surfaces opposite one another at least partially within the opening during the damascene process. The surfaces are curvilinear with respect to a horizontal cross-section. The present embodiment then recites forming a first copper region having a curvilinear surface proximate one of the surfaces of the dielectric region during the damascene process. The present embodiment then recites forming a second copper region having a curvilinear surface proximate a second surface of the dielectric region during the damascene process. In so doing, the dielectric region forms a dielectric barrier between the first copper region and the second copper region such that the vertical cylindrical MIM capacitor is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.