LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliability
US6548839B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2002 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Feb 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/257
Abstract
An LDMOS array includes an array of alternating source regions and drain regions formed in a semiconductor substrate to define a checkerboard pattern of source and drain regions. A source contact is formed in electrical contact with each of the source regions in the array to connect the source regions in parallel. A drain contact is formed in electrical contact with each of the drain regions in the array to connect the drain regions in parallel. A drain ring is formed around the periphery of the checkerboard pattern and in electrical contact with the drain contact, providing redistribution of the current flow within the LDMOS array and thereby allowing safer hot carrier operation at higher biases than with the conventional layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.