Apparatus and method for analyzing functional failures in integrated circuits
US6549022B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 2, 2000 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | May 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/308
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus and method are presented for identifying and mapping functional failures in an integrated circuit (IC) due to timing errors therein based on the generation of functional failures in the IC. This is done by providing a set of input test vectors to the IC and adjusting one or more: of the IC voltage, temperature or clock frequency; the rate at which the test vectors are provided to the IC; or the power level of a focused laser beam used to probe the IC and produce localized heating which changes the incidence of the functional failures in the IC which can be sensed for locating the IC circuit elements responsible for the functional failures. The present invention has applications for optimizing the design and fabrication of ICs, for failure analysis, and for qualification or validation testing of ICs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.