Configuration and process for testing a multiplicity of semiconductor chips on a wafer plane
US6549028B1 · kind B1 · utility
2Cited by
4References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 2, 2000 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Aug 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Arrangement and method for testing a multiplicity of semiconductor chips at the wafer level The invention relates to an arrangement and a method for testing a multiplicity of semiconductor chips (7) at the wafer level, in which an intermediate wiring plane (10) with a global test bus (12) and test pads (11) is applied to the surface of the wafer (6).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.