Integrated test structure and method for verification of microelectronic devices
US6549150B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2001 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Sep 17, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated test structure adapted to facilitate manufacturing verification of microelectronic devices such as Digital to Analog Converters (DAC) is disclosed. The test circuitry and the Circuit Under Test (CUT) are placed on an IC along with an arbitrary amount of digital logic, which drives the input of the CUT. These inputs are translated into an analog output. During a manufacturing test, this output is measured in order to determine that the IC has been manufactured correctly. The analog input of the circuit is coupled to the analog output of the DAC. The digital output of the test circuitry is coupled to the digital logic on the IC. This configuration comprises a Built In Self Test (BIST) structure. The invention allows BIST by eliminating the need to measure the analog output of the DAC external to the IC, and enables testing the CUT by using standard digital BIST techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.