Method in integrating clock tree synthesis and timing optimization for an integrated circuit design
US6550044B1 · kind B1 · utility
31Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2001 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Jun 19, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of synthesizing a clock tree for an integrated circuit design is disclosed that includes the steps of constructing an initial balanced clock tree for an integrated circuit design; calculating a clock arrival time for each clock driven cell in the initial clock tree; performing a timing analysis from the clock arrival time calculated for each clock driven cell; and performing a skew optimization concurrently with the timing analysis to correct timing violations discovered by the timing analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.