Changing clock delays in an integrated circuit for skew optimization
US6550045B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Apr 15, 2003 |
| Priority date | — |
| Expiry date | Nov 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Clock delays are changed in a clock network of an ASIC. Global skew optimization is achieved by restructuring a clock domain to balance clock delays in the domain, and by equalizing clock delays of several domains of a group that have timing paths between them. Clock delays are equalized using buffer chains affecting all leaves of the respective domain, and an additional delay coefficient that equalizes clock delay. The clock insertion delays are changed for each group by restructuring the buffers in the group, based on both the data and clock logics to optimize the paths. Local skew optimization is achieved by restructuring the clock domain using a heuristic algorithm and re-ordering the buffers of the domain. A computer program enables a processor to carry out the processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.