Method for potential controlled electroplating of fine patterns on semiconductor wafers
US6551483B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | May 10, 2021 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC25D7/123
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.