Low temperature process for a thin film transistor
US6551885B1 · kind B1 · utility
152Cited by
68References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 9, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Feb 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
A method of manufacturing an integrated circuit utilizes a thin film substrate and a high-k gate dielectric. The method includes providing a mask structure on a top surface of the thin film, depositing a semiconductor material above the top surface of the thin film and the mask structure, removing the semiconductor material to a level below the top surface of the mask structure, siliciding the semiconductor material, and providing a gate structure in an aperture formed by removing the mask structure. The transistor can be a fully depleted transistor having material for siliciding source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.