Mos transistor with dual metal gate structure
US6552377B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 2000 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Mar 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method for making a ULSI MOSFET includes depositing a high-k gate insulator on a silicon substrate and then depositing a field oxide layer over the gate insulator. The field oxide layer is masked with photoresist and the photoresist patterned to establish first gate windows, and the oxide below the windows is then etched away to establish first gate voids in the oxide. The first gate voids are filled with a first metallic gate electrode material that is suitable for establishing a gate electrode of, e.g., an N-channel MOSFET. Second gate voids are similarly made in the oxide and filled with a second gate electrode material that is suitable for establishing a gate electrode of, e.g., an P-channel MOSFET or another N-channel MOSFET having a different threshold voltage than the first MOSFET. With this structure, plural threshold design voltages are supported in a single ULSI chip that uses high-k gate insulator technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.