DRAM memory capacitor having three-layer dielectric, and method for its production

US6552385B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Gerhard Beitel · Kamakura, JP
• Martin Franosch · Munich, DE
• Thomas Haneder · Hersbruck, DE
• Gerrit Lange · Denzlingen, DE
• Hans Reisinger · Grünwald, DE
• Herbert Schafer · Höhenkirchen-Siegertsbrunn, DE
• Stephan Schlamminger · Rockville, US
• Hermann Wendt · Grasbrunn, DE

Key dates

• Filing date: Jan 8, 2001
• Grant date: Apr 22, 2003
• Expiry date: Jan 8, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/02266
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A DRAM capacitor is described that contains a BaSrTiO3 (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential trough in which electrons can be permanently trapped.