Circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory
US6552921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2002 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Jan 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit to simulate the polarization relaxation phenomenon of the ferroelectric memory. The circuit has a MOS transistor, a ferroelectric capacitor, a capacitor, and a relaxation voltage source. The gate of the MOS transistor is coupled to a word line and the source of the MOS transistor is coupled to a bit line. A first electrode of the ferroelectric capacitor is coupled to the drain of the MOS transistor and the second electrode of the ferroelectric capacitor is coupled to a plate line. A first electrode of the capacitor is coupled to the drain of the MOS transistor. A first electrode of the relaxation voltage source is coupled to the second electrode of the capacitor, and the second electrode of the relaxation voltage source is coupled to a ground. The capacitance of the capacitor mentioned above is selectively far smaller than the capacitance of the bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.