Two-step chemical-mechanical planarization for damascene structures on semiconductor wafers
US6555466B1 · kind B1 · utility
4Cited by
10References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 1999 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Mar 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of improving planarity of semiconductor wafer surfaces containing damascene and dual-damascene circuitry using chemical-mechanical polishing techniques. The method includes using a first polishing step to substantially remove excess surface metal up to a detected end point. After rinsing, a second step of chemical-mechanical polishing is applied, using a second slurry that has a higher selectivity for dielectric than metal, preferably from 1.8 to 4 or more times greater. The second step of polishing, in accordance with the invention, has been found to substantially eliminate dishing and improve planarity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.