Method and apparatus for determining digital delay line entry point
US6556489B2 · kind B2 · utility
57Cited by
4References
65Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 6, 2001 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Aug 6, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, a counter is coupled to the phase detector of the DLL to track the entry point of the delay line. The entry point information can be taken over a variety of voltages, temperatures, and frequencies to characterize the DLL. The counter may be located on the synchronous device or external to the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.