Patent · US Expired

System for testing fast synchronous semiconductor circuits

US6556492B2 · kind B2 · utility

19Cited by

5References

10Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Wolfgang Ernst · Munich, DE
Gunnar Krause · Munich, DE
Justus Kuhn · Birkenfeld, DE
Jens Lüpke · Hersbruck, DE
Jochen Müller · Hersbruck, DE
Peter Pöchmüller · Birkenfeld, DE
Michael Schittenhelm · Poing, DE

Key dates

Filing date	Jul 18, 2001
Grant date	Apr 29, 2003
Priority date	—
Expiry date	Jul 18, 2021

Classification

Technology area (CPC G)Physics
CPC primaryG11C29/56
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.