Justus Kuhn
19Patents
7h-index
19Co-inventors
55Inventor score
Filing activity: May 18, 2001 → Sep 15, 2005
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6954871B2 | Method of matching different signal propagation times between a controller and at least two processing units, and a computer system | Physics | 32 | Expired |
| US6556492B2 | System for testing fast synchronous semiconductor circuits | Physics | 19 | Expired |
| US6744272B2 | Test circuit | Physics | 12 | Expired |
| US6762611B2 | Test configuration and test method for testing a plurality of integrated circuits in parallel | Physics | 9 | Expired |
| US6515319B2 | Field-effect-controlled transistor and method for fabricating the transistor | Electricity | 9 | Expired |
| US6721904B2 | System for testing fast integrated digital circuits, in particular semiconductor memory modules | Physics | 9 | Expired |
| US6871306B2 | Method and device for reading and for checking the time position of data response signals read out from a memory module to be tested | Physics | 7 | Expired |
| US6853206B2 | Method and probe card configuration for testing a plurality of integrated circuits in parallel | Physics | 5 | Expired |
| US6618305B2 | Test circuit for testing a circuit | Physics | 4 | Expired |
| US6865707B2 | Test data generator | Physics | 3 | Expired |
| US7043653B2 | Method and apparatus for synchronous signal transmission between at least two logic or memory components | Physics | 3 | Expired |
| US6910161B2 | Device and method for reducing the number of addresses of faulty memory cells | Physics | 3 | Expired |
| US7117404B2 | Test circuit for testing a synchronous memory circuit | Physics | 3 | Expired |
| US7307895B2 | Self test for the phase angle of the data read clock signal DQS | Physics | 1 | Expired |
| US6862702B2 | Address counter for addressing synchronous high-frequency digital circuits, in particular memory devices | Physics | 1 | Expired |
| US7062690B2 | System for testing fast synchronous digital circuits, particularly semiconductor memory chips | Physics | 1 | Expired |
| US6839397B2 | Circuit configuration for generating control signals for testing high-frequency synchronous digital circuits | Physics | 1 | Expired |
| US6957373B2 | Address generator for generating addresses for testing a circuit | Physics | 0 | Expired |
| US7117403B2 | Method and device for generating digital signal patterns | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.