Method for forming three dimensional semiconductor structure and three dimensional capacitor
US6559004B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2001 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Dec 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a three dimensional semiconductor structure which has vertical capacitor(s) but not horizontal capacitor(s). The method essentially at least includes these steps of forming bottom plates within dielectric layers, forming another dielectric layer over bottom plates, removing all dielectric layers over bottom plates, forming optional liner(s) and capacitor dielectric layers on bottom plates, and forming top plates over capacitor dielectric layers. Note that shape of bottom plates is alike to the bottom connection and verticle fingers, also note that each gap within bottom plates is filled by both capacitor dielectric layer and top plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.