System and method for facilitating detection of defects on a wafer
US6559457B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2000 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Mar 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/2817
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention relates to detecting defects on a wafer. A wafer stage includes markings which are used to form a reference coordinate system. The wafer is positioned on the wafer stage and the wafer is scanned to detect a defect on the wafer. The position of the detected defect is mapped relative to the reference coordinate system of the stage. The location of a reference point on the wafer also is determined in the reference coordinate system. The position of the defect is determined relative to the reference point on the wafer so as to facilitate repeatedly locating the defect on the wafer as the wafer is loaded and reloaded into inspection and processing tools.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.