Ferroelectric and high dielectric constant transistors
US6559469B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2000 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Jan 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
An integrated circuit includes a layered superlattice material having the formula A1w1+a1A2w2+a2 . . . Ajwj+ajS1x1+s1S2x2+s2 . . . Skxk+skB1y1+b1B2y2+b2 . . . Blyl+blQz−q, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . B1 represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in ferroelectric FETs in non-volatile memories. Others are high dielectric constant materials that do not degrade or break down over long periods of use and are applied as the gate insulator in volatile memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.