Compact ballasting region design for snapback N-MOS ESD protection structure using multiple local N+ region blocking
US6559507B1 · kind B1 · utility
9Cited by
2References
17Claims
0Family size
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Key dates
| Filing date | Jun 29, 2001 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Jun 29, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
In a n+ snapback device, saturation current is limited by using one or more NLDD current blocking regions. This limits the snapback saturation current, while avoiding current stratification by providing for current spreading, and thus avoiding localized heating problems
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.