Andy Strachan
27Patents
8h-index
24Co-inventors
71Inventor score
Filing activity: May 8, 2001 → Nov 4, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6566710B1 | Power MOSFET cell with a crossed bar shaped body contact area | Electricity | 37 | Expired |
| US6586317B1 | Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage | Emerging Cross-Sectional Technologies | 27 | Expired |
| US6727547B1 | Method and device for improving hot carrier reliability of an LDMOS transistor using drain ring over-drive bias | Electricity | 11 | Expired |
| US6815797B1 | Silicide bridged anti-fuse | Electricity | 11 | Expired |
| US6946706B1 | LDMOS transistor structure for improving hot carrier reliability | Electricity | 11 | Expired |
| US6806529B1 | Memory cell with a capacitive structure as a control gate and method of forming the memory cell | Electricity | 10 | Expired |
| US6559507B1 | Compact ballasting region design for snapback N-MOS ESD protection structure using multiple local N+ region blocking | Electricity | 9 | Expired |
| US7105373B1 | Vertical photodiode with heavily-doped regions of alternating conductivity types | Emerging Cross-Sectional Technologies | 8 | Expired |
| US7214992B1 | Multi-source, multi-gate MOS transistor with a drain region that is wider than the source regions | Electricity | 7 | Expired |
| US7298159B1 | Method of measuring the leakage current of a deep trench isolation structure | Physics | 7 | Expired |
| US7507607B1 | Method of forming a silicide bridged anti-fuse with a tungsten plug metalization process | Electricity | 7 | Active |
| US6919588B1 | High-voltage silicon controlled rectifier structure with improved punch through resistance | Electricity | 6 | Expired |
| US6979879B1 | Trim zener using double poly process | Electricity | 5 | Expired |
| US7192857B1 | Method of forming a semiconductor structure with non-uniform metal widths | Electricity | 4 | Expired |
| US7960998B2 | Electrical test structure and method for characterization of deep trench sidewall reliability | Electricity | 3 | Active |
| US6844585B1 | Circuit and method of forming the circuit having subsurface conductors | Electricity | 2 | Expired |
| US7238553B1 | Method of forming a high-voltage silicon controlled rectifier structure with improved punch through resistance | Electricity | 2 | Expired |
| US6933562B1 | Power transistor structure with non-uniform metal widths | Electricity | 2 | Expired |
| US9865584B1 | Contact array optimization for ESD devices | Electricity | 1 | Active |
| US7488647B1 | System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device | Electricity | 1 | Expired |
| US6864582B1 | Semiconductor interconnect and method of providing interconnect using a contact region | Electricity | 1 | Expired |
| US7714355B1 | Method of controlling the breakdown voltage of BSCRs and BJT clamps | Electricity | 1 | Active |
| US7037814B1 | Single mask control of doping levels | Electricity | 1 | Expired |
| US7479435B1 | Method of forming a circuit having subsurface conductors | Electricity | 0 | Expired |
| US7989883B1 | System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.