Stacked package structure of image sensor
US6559539B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jan 24, 2001 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Jan 24, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1627
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked package structure of an image sensor used for electrically connecting to a printed circuit board includes a substrate, an image sensing chip, an integrated circuit, and a transparent layer. The substrate has a first surface and a second surface. The first surface is formed with signal input terminals. The second surface is formed with signal input terminals and signal output terminals for electrically connecting to the printed circuit board. The image sensing chip is mounted on the first surface of the substrate and is electrically to the signal input terminals of the substrate. The integrated circuit is arranged on the second surface of the substrate and is electrically connected to the signal input terminals of the substrate. The transparent layer covers over the image sensing chip, which can receive the image signals via the transparent layer and convert the image signals into electrical signals that are to be transmitted to the substrate. Thus, the image sensing chip of the image sensing product and integrated circuit can be integrally packaged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.