Chip scale packaging on CTE matched printed wiring boards
US6560108B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2000 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Feb 16, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit assembly has a heat sink assembly and a chip scale package assembly. The chip scale package assembly has an integrated circuit die coupled to a first printed wiring board. The heat sink assembly has an integrated circuit die coupled to a second printed wiring board. Preferably, the heat sink assembly and the chip scale package assembly are assembled separately then assembled together. The circuit pads on the first printed wiring board correspond with circuit pads on the second printed wiring board. The circuit pads may be coupled together by solder or adhesive bonding. The circuit pads on the first printed wiring board may have solder balls formed of high temperature solder that do not melt when the heat sink assembly is assembled with chip scale package assembly. The solder balls allow chip scale package assembly to maintain a predetermined distance from the circuit pads on the second printed wiring board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.