Process for forming shallow isolating regions in an integrated circuit and an integrated circuit thus formed
US6561839B2 · kind B2 · utility
0Cited by
11References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2001 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Aug 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76213
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The formation of the isolating region includes ion implantation in the voluminal part, followed by annealing of said implanted voluminal part (7) of the substrate (1).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.