Apparatus and method for delamination-resistant, array type molding of increased mold cap size laminate packages
US6562272B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2000 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | May 29, 2021 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB29C2045/4063
- WIPO fieldOther special machines
- WIPO sectorMechanical engineering
Abstract
An apparatus and method for providing delamination-resistant, array type molding of chip laminate packages such that larger chip array block sizes may be employed. An advanced mold die provides multiple wells for the formation of ejector pin tabs to be formed integrally to the mold cap of a chip laminate package. The die further provides for an ejector pin hole to be located at each ejector pin tab such that the ejector pins, when pressed for release of the laminate package from the mold die, bear against the integrally formed pin tabs rather than against the substrate of the chip/substrate assembly. The placement of the ejector pins for bearing against the pin tabs precludes the loading of the interface within the laminate package between the mold cap and the chip/substrate assembly. Substantially reduced delamination of the chip laminate package is achieved allowing for the use of larger chip array block sizes and providing for a substantial reduction in chip laminate package moisture sensitivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.