Vani Verma
13Patents
6h-index
7Co-inventors
55Inventor score
Filing activity: Feb 26, 1999 → Jun 21, 2010
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6731011B2 | Memory module having interconnected and stacked integrated circuits | Electricity | 31 | Expired |
| US7005730B2 | Memory module having interconnected and stacked integrated circuits | Electricity | 26 | Expired |
| US6331728A | High reliability lead frame and packaging technology containing the same | Electricity | 13 | Expired |
| US7432599B2 | Memory module having interconnected and stacked integrated circuits | Electricity | 10 | Active |
| US7105377B1 | Method and system for universal packaging in conjunction with a back-end integrated circuit manufacturing process | Electricity | 9 | Expired |
| US6562272B1 | Apparatus and method for delamination-resistant, array type molding of increased mold cap size laminate packages | Performing Operations; Transporting | 8 | Expired |
| US6853202B1 | Non-stick detection method and mechanism for array molded laminate packages | Electricity | 5 | Expired |
| US6576491B1 | Methods for producing high reliability lead frame and packaging semiconductor die using such lead frame | Electricity | 5 | Expired |
| US8395246B2 | Two-sided die in a four-sided leadframe based package | Electricity | 5 | Active |
| US7391104B1 | Non-stick detection method and mechanism for array molded laminate packages | Electricity | 5 | Expired |
| US6730532B1 | Method and system for universal packaging in conjunction with a back-end integrated circuit manufacturing process | Emerging Cross-Sectional Technologies | 4 | Expired |
| US8349655B2 | Method of fabricating a two-sided die in a four-sided leadframe based package | Electricity | 0 | Active |
| US8058099B2 | Method of fabricating a two-sided die in a four-sided leadframe based package | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.