Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology

US6562665B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventor

• Bin Yu · Cupertino, US

Key dates

• Filing date: Oct 16, 2000
• Grant date: May 13, 2003
• Expiry date: May 30, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/673

Abstract

For fabricating a field effect transistor, a pillar of semiconductor material is formed, a recess is formed in the top surface of the pillar along the length of the pillar, a gate dielectric material is deposited on any exposed surface of the semiconductor material of the pillar including at the top surface and the first and second side surfaces of the pillar and at the sidewalls and the bottom wall of the recess, for a gate length along the length of the pillar. In addition, a gate electrode material is deposited on the gate dielectric material to surround the pillar at the top surface and the first and second side surfaces of the pillar and to fill the recess, for the gate length of the pillar. A drain and source dopant is implanted into exposed regions of the pillar to form a drain of the field effect transistor on a first side of the gate electrode material along the length of the pillar and to form a source of the field effect transistor on a second side of the gate electrode material along the length of the pillar.