Integrated circuits with reduced substrate capacitance

US6562666B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Heemyong Park · Lagrangeville, US
• Fariborz Assaderaghi · Jefferson Valley, US
• Jack A. Mandelman · Stormville, US
• Ghavam G. Shahidi · Pound Ridge, US
• Lawrence F. Wagner, Jr. · Fishkill, US

Key dates

• Filing date: Oct 31, 2000
• Grant date: May 13, 2003
• Expiry date: Nov 24, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

Capacitance between source/drain and p-type substrate in SOI CMOS circuits is reduced by implanting an n-type layer below the oxide layer, thereby forming a fully depleted region that adds to the thickness of the oxide layer, while creating a junction capacitance region that reduces the total device to substrate capacitance.