Method of fabricating a self-aligned split gate flash memory cell

US6562673B2 · kind B2 · utility

Assignee

• NANYA TECHNOLOGY CORPORATION · TW

Inventor

• Chi-Hui Lin · Taipei, TW

Key dates

• Filing date: Sep 7, 2001
• Grant date: May 13, 2003
• Expiry date: Oct 13, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/30

Abstract

A method of fabricating a memory cell of self-aligned split gate flash memory first provides a substrate having an active area. A first gate insulating layer, a conductive layer and a buffer layer are formed within the active area. A portion of the buffer layer is removed to form a first opening. A buffer spacer is formed on the side walls of the first opening. A portion of the conductive layer and first gate insulating layer under the first opening are removed to form a second opening. The contact spacers, the source region and the contact plug are formed in the second opening in sequence. After the buffer spacers are removed, a third opening is formed. The bottom surface of the third opening and the top surface of the contact plug are oxidized to form the oxide layers. Another buffer spacers fill the third opening. The remaining buffer layer is removed to form the fourth opening. The conductive layer under the bottom of the fourth opening is removed, except the portion under the oxide layer, to form the floating gates. After the formation of a second gate insulating layer, the control gates and the control gate spacers are formed in sequence.